HD6417705 Datasheet, PDF (142/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

4.2.1 Cache Control Register 1 (CCR1)
The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which
invalidates all cache entries), and WT and CB bits (which select either write-through mode or
write-back mode). Programs that change the contents of the CCR1 register should be placed in
address space that is not cached.
Bit
31 to 4
Bit
Name
—
3
CF
2
CB
1
WT
0
CE
Initial
Value
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cache Flush
Writing 1 flushes all cache entries (clears the V, U,
and LRU bits of all cache entries to 0). This bit is
always read as 0. Write-back to external memory is
not performed when the cache is flushed.
Write-Back
Indicates the cache’s operating mode for space P1.
0: Write-through mode
1: Write-back mode
Write-Through
Indicates the cache’s operating mode for spaces P0,
U0, and P3.
0: Write-back mode
1: Write-through mode
Cache Enable
Indicates whether the cache function is used.
0: The cache function is not used.
1: The cache function is used.
Rev. 2.00, 09/03, page 96 of 690