HD6417705 Datasheet, PDF (295/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
2
AE
0
R/(W)^* Address Error Flag
Indicates that an address error occurred by the DMAC. If this
bit is set, DMA transfer is not enabled even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1. This bit can
only be cleared by writing 0 after reading 1.
0: No DMAC address error
[Clearing conditions]
• Writing 0 after reading AE = 1
• Power-on reset
• Manual reset
1: DMAC address error. DMA transfer disabled.
[Setting condition]
DMAC address error occurrence
1
NMIF 0
R/(W)^* NMI Flag
Indicates that an NMI interrupt occurred. If this bit is set, DMA
transfer is not enabled even if the DE bit in CHCR and the
DME bit in DMAOR are set to 1. This bit can only be cleared
by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can be
done in one transfer unit. When the DMAC is not in operation,
the NMIF bit is set to 1 even if the NMI interrupt was input.
0: No NMI interrupt
[Clearing conditions]
• Writing 0 after reading NMIF = 1
• Power-on reset
• Manual reset
1: NMI input. DMA transfer disabled.
[Setting condition]
NMI interrupt occurrence
0
DME 0
R/W DMA Master Enable
Enables or disables DMA transfers on all channels. If the
DME bit and the DE bit in CHCR are set to 1, DMA transfers
are enabled. In this time, all of the bits TE in CHCR, NMIF in
DMAOR, and AE must be 0. If this bit is cleared during
transfer, transfers in all the channels can be terminated.
0: Disable DMA transfers on all channels
1: Enable DMA transfers on all channels
Note: * Only 0 can be written for clearing the flags.
Rev. 2.00, 09/03, page 249 of 690