HD6417705 Datasheet, PDF (118/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

In single virtual memory mode, the ASID is used to provide memory protection for processes
running simultaneously and using the virtual address space exclusively (see section 3.3.3, TLB
Address Comparison).
3.2 Register Descriptions
There are four registers for MMU processing. These are all on-chip module control registers, so
they are located in address space area P4 and can only be accessed from privileged mode by
specifying the address.
The MMU has the following registers. Refer to section 24, List of Registers, for the addresses and
access size for these registers.
• Page table entry register high (PTEH)
• Page table entry register low (PTEL)
• Translation table base register (TTB)
• MMU control register (MMUCR)
3.2.1 Page Table Entry Register High (PTEH)
The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual address
at which the exception is generated in case of an MMU exception or address error exception.
When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case
the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the
ASID, software sets the number of the currently executing process. The VPN and ASID are
recorded in the TLB by the LDTLB instruction.
A program that modifies the ASID in PTEH should be allocated in the P1 or P2 areas.
Bit
31 to 10
9, 8
Bit
Name
VPN

7 to 0
ASID
Initial
Value

0

R/W
R/W
R
R/W
Description
Number of Virtual Page
Reserved
These bits are always read as 0. The write value
should always be 0.
Address Space Identifier
Rev. 2.00, 09/03, page 72 of 690