HD6417705 Datasheet, PDF (364/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

12.4 Operation
Each of the three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register
(TCOR). The TCNT counts down. The auto-reload function enables synchronized counting and
counting by external events. Channel 2 has an input capture function.
12.4.1 Counter Operation
When the STR0 to STR2 bits in the timer start register (TSTR) are set to 1, the corresponding
timer counter (TCNT) starts counting. When a TCNT underflows, the UNF flag of the
corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an
interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT
and the down-count operation is continued.
Count Operation Setting Procedure: An example of the procedure for setting the count
operation is shown in figure 12.2.
Select operation
Select counter
clock
(1)
Set underflow
interrupt generation
(2)
When using input
capture function
Set input capture ₍₃₎
interrupt generation
Set timer constant
register
(4)
(1) Select the counter clock with the TPSC0-TPSC2
bits in the timer control register. If the external
clock is selected, select its edge with the CKEG1
and CKEG0 bits in the timer control register.
(2) Use the UNIE bit in the timer control register to set
whether to generate an interrupt when timer
counter underflows.
(3) When using the input capture function, set the
ICPE bits in the timer control register, including
the choice of whether or not to use the interrupt
function (channel 2 only).
(4) Set a value in the timer constant register
(the cycle is the set value plus 1).
(5) Set the initial value in the timer counter.
(6) Set the STR bit in the timer start register to 1 to
start operation.
Initialize timer
counter
(5)
Start counting
(6)
Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it.
If interrupts are enabled without clearing the flag, another interrupt will be generated.
Figure 12.2 Setting Count Operation
Rev. 2.00, 09/03, page 318 of 690