HD6417705 Datasheet, PDF (414/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
0
START
1
R/W Start Bit
Halts and restarts the counter (clock).
0: Second/minute/hour/day/week/month/year
counter halts.^*
1: Second/minute/hour/day/week/month/year
counter runs normally.^*
Note: * The 64-Hz counter always runs unless
stopped with the RTCEN bit.
15.3.18 RTC Control Register 3 (RCR3)
The RTC control register 3 (RCR3) is an 8-bit readable/writable register that controls the
comparison between the BCD-coded year section counter RYRCNT of the RTC and the year
alarm register RYRAR.
Bit
7
6 to 0
Bit Name
YAEN
Initial Value R/W
0
R/W
—
0
R
Description
Year Alarm Enable
When this bit is set to 1, the year alarm register
(RYRAR) is compared with the year counter
(RYRCNT). For alarm registers RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and
RMONAR, a comparison with the corresponding
counter value is performed for those whose ENB
bit is set to 1, and for RCR3, a comparison is
performed when this bit is set to 1. If all of those
match, an RTC alarm interrupt is generated.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00, 09/03, page 368 of 690