HD6417705 Datasheet, PDF (39/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 25.3 CKIO Clock Input Timing .................................................................................. 632
Figure 25.4 CKIO Clock Output Timing ................................................................................ 632
Figure 25.5 Power-On Oscillation Settling Time .................................................................... 633
Figure 25.6 Oscillation Settling Time at Standby Return (Return by Reset) ............................ 633
Figure 25.7 Oscillation Settling Time at Standby Return (Return by NMI) ............................. 633
IRL3 IRL0 Figure 25.8 Oscillation Settling Time at Standby Return
(Return by IRQ5 to IRQ0, PINT15 to PINT0, and
to )......................... 634
Figure 25.9 PLL Synchronization Settling Time by Reset or NMI .......................................... 634
Figure 25.10 PLL Synchronization Settling Time by IRQ/IRL, PINT Interrupts ..................... 635
Figure 25.11 PLL Synchronization Settling Time when Frequency Multiplication
Ratio Modified ................................................................................................. 635
Figure 25.12 Reset Input Timing ........................................................................................... 637
Figure 25.13 Interrupt Signal Input Timing ............................................................................ 637
Figure 25.14 Bus Release Timing .......................................................................................... 637
Figure 25.15 Pin Drive Timing at Standby ............................................................................. 638
Figure 25.16 Basic Bus Cycle (No Wait) ............................................................................... 640
Figure 25.17 Basic Bus Cycle (One Software Wait) ............................................................... 641
Figure 25.18 Basic Bus Cycle (One External Wait) ................................................................ 642
Figure 25.19 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM Bit = 0),
No Idle Cycle Setting) ...................................................................................... 643
Figure 25.20 Address/Data Multiplex I/O Bus Cycle
(Three Address Cycles, One Software Wait, One External Wait) ........................ 644
Figure 25.21 Burst ROM Read Cycle
(One Access Wait, One External Wait, One Burst Wait, Two Bursts) ................. 645
Figure 25.22 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 1 Cycle)............... 646
Figure 25.23 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 2 Cycle)............... 647
Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
(Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 2 Cycle)............... 648
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
(Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 1 Cycle)............... 649
Figure 25.26 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRWL = 2 Cycle) ................................................................... 650
Figure 25.27 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRCD = 3 Cycle, TRWL = 2 Cycle) ....................................... 651
Figure 25.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
(Auto Precharge, TRCD = 1 Cycle, TRWL = 2 Cycle) ....................................... 652
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
(Auto Precharge, TRCD = 2 Cycle, TRWL = 2 Cycle) ....................................... 653
Figure 25.30 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: ACTV + READ Commands, CAS Latency = 2,
TRCD = 1 Cycle).............................................................................................. 654
Rev. 2.00, 09/03, page xxxix of xlvi