HD6417705 Datasheet, PDF (608/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

22.3.7 Usage Examples
Break Condition Specified for an L Bus Instruction Fetch Cycle
1. Register specifications
BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300400
Specified conditions: Channel A/channel B independent mode
• Channel A
Address:
H'00000404, Address mask: H'00000000
Bus cycle:
L bus/instruction fetch (after instruction execution)/read (operand size
is not included in the condition)
The ASID check is not included.
• Channel B
Address:
H'00008010, Address mask: H'00000006
Data:
H'00000000, Data mask: H'00000000
Bus cycle:
L bus/instruction fetch (before instruction execution)/read (operand size
is not included in the condition)
The ASID check is not included.
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
2. Register specifications
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequential mode
• Channel A
Address:
H'00037226, Address mask: H'00000000, ASID = H'80
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
• Channel B
Address:
H'0003722E, Address mask: H'00000000, ASID = H'70
Data:
H'00000000, Data mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
After an instruction with ASID = H'80 and address H'00037226 is executed, a user break
occurs before an instruction with ASID = H'70 and address H'0003722E is executed.
Rev. 2.00, 09/03, page 562 of 690