HD6417705 Datasheet, PDF (431/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

16.3.6 Serial Control Register (SCSCR)
SCSCR is a 16-bit readable/writable register that enables or disables the SCIF transfer operations
and interrupt requests, and selects the serial clock source.
Bit
Initial
Bit
Name Value R/W Description
15 to 12 
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
11
TSIE 0
R/W Transmit Data Stop Interrupt Enable
Enables or disables generation of a transmit-data-stop
interrupt when the TSE bit in SCFCR is enabled and the
TSF flag in SCSSR is set to 1.
0: Transmit-data-stop interrupt disabled^*
10
ERIE 0
1: Transmit-data-stop interrupt enabled
Note: * The interrupt request is cleared by clearing the
TSF flag to 0 after reading 1 from it or clearing
the TSIE bit to 0.
R/W Receive Error Interrupt Enable
Enables or disables generation of a receive-error
(framing or parity error) interrupt when the ER flag in
SCSSR is set to 1.
0: Receive-error interrupt disabled^*
1: Receive-error interrupt enabled
Note: * The interrupt request is cleared by clearing the
ER flag to 0 after reading 1 from it or clearing the
ERIE bit to 0.
Rev. 2.00, 09/03, page 385 of 690