HD6417705 Datasheet, PDF (359/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

12.3.2 Timer Control Registers (TCR)
TCR are 16-bit readable/writable registers that control the timer counters (TCNT) and interrupts.
TCR control the issuance of interrupts when the flag indicating timer counter (TCNT) underflow
has been set to 1, and also carry out counter clock selection. When the external clock has been
selected, they also select its edge.
Only TCR_2 controls the input capture function and the issuance of interrupts during input
capture.
TCR_0 and TCR_1:
Bit Bit Name Initial Value
15 to 9 
0
8
UNF
0
7, 6 
0
5
UNIE
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)^* Underflow Flag
Status flag that indicates occurrence of a TCNT
underflow.
0: TCNT has not underflowed
[Clearing condition]
0 is written to UNF
1: TCNT has underflowed
[Setting condition]
TCNT underflows
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Underflow Interrupt Control
Controls enabling of interrupt generation when the
status flag (UNF) indicating TCNT underflow has been
set to 1.
0: Interrupt due to UNF (TUNI) is disabled
1: Interrupt due to UNF (TUNI) is enabled
Rev. 2.00, 09/03, page 313 of 690