HD6417705 Datasheet, PDF (206/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
15

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
14
TYPE2 0
R/W Memory Type
13
TYPE1 0
R/W Specify the type of memory connected to a space.
12
TYPE0 0
R/W 000: Normal space
001: Burst ROM
010: Address/data multiplex I/O (MPX)
011: Byte-selection SRAM
100: SDRAM
101: Setting prohibited
110: Setting prohibited
11

111: Setting prohibited
Note:
SDRAM can be specified only in area 2 and area 3. If
SDRAM is connected to only one area, SDRAM
should be specified for area 3. In this case area 2
should be specified as normal space. Burst ROM can
be specified only in area 0 and area 4. Address/data
multiplex I/O (MPX) can be specified only in area 5B.
Byte-selection SRAM can be specified only in area 4
and area 5B.
0
R
Reserved
This bit is always read as 0. The write value should always be
0.
10
BSZ1 1
R/W Data Bus Size
9
BSZ0 1
R/W Specify the data bus sizes of spaces.
The data bus sizes of areas 2, 3, 4 and 5A are shown below.
00: Setting prohibited.
01: 8-bit size
10: 16-bit size
11: 32-bit size
The data bus sizes of areas 5B, 6A, and 6B are shown below.
00: Setting prohibited.
01: 8-bit size
10: 16-bit size
11: Setting Prohibited
Rev. 2.00, 09/03, page 160 of 690