HD6417705 Datasheet, PDF (116/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For
more information, see section 4.4, Memory-Mapped Cache.
The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more
information, see section 4.4, Memory-Mapped Cache.
The area from H'F200 0000 to H'F2FF FFFF is for direct access to the TLB address array. For
more information, see section 3.6, Memory-Mapped TLB.
The area from H'F300 0000 to H'F3FF FFFF is for direct access to the TLB data array. For more
information, see section 3.6, Memory-Mapped TLB.
The area from H'FC00 0000 to H'FFFF FFFF is reserved for the on-chip module control registers.
For more information, see section 24, List of Registers.
Physical Address Space: This LSI supports a 29-bit physical address space. As shown in figure
3.5, the physical address space is divided into eight areas. Area 1 is mapped to the on-chip module
control register area. Area 7 is reserved.
For details on physical address space, refer to section 7, Bus State Controller (BSC).
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF
Area 0
Area 1
(On-Chip module
control register)
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
(Reserved Area)
Figure 3.5 External Memory Space
Rev. 2.00, 09/03, page 70 of 690