HD6417705 Datasheet, PDF (102/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 2.8 Logic Operation Instructions
Instruction
AND
Rm,Rn
AND
#imm,R0
AND.B
#imm,@(R0,
GBR)
NOT
Rm,Rn
OR
Rm,Rn
OR
#imm,R0
OR.B
#imm,@(R0,
GBR)
TAS.B @Rn
TST
Rm,Rn
TST
#imm,R0
TST.B
XOR
XOR
XOR.B
#imm,@(R0,
GBR)
Rm,Rn
#imm,R0
#imm,@(R0,
GBR)
Instruction
Code
Operation
Privileged
Mode
Cycles T Bit
0010nnnnmmmm1001Rn & Rm → Rn
–
1
–
11001001iiiiiiii
R0 & imm → R0
–
1
–
11001101iiiiiiii
(R0+GBR) & imm → (R0+GBR) –
3
–
0110nnnnmmmm0111^~Rm → Rn
–
0010nnnnmmmm1011RnRm → Rn
–
11001011iiiiiiii
R0imm → R0
–
11001111iiiiiiii
(R0+GBR)imm → (R0+GBR) –
1
–
1
–
1
–
3
–
0100nnnn00011011 If (Rn) is 0, 1 → T; 1 → MSB of –
(Rn)
0010nnnnmmmm1000Rn & Rm; if the result is 0, 1 → T –
11001000iiiiiiii
R0 & imm; if the result is 0, 1 → T –
11001100iiiiiiii
(R0 + GBR) & imm; if the result is –
0, 1 → T
0010nnnnmmmm1010Rn ^ Rm → Rn
–
11001010iiiiiiii
R0 ^ imm → R0
–
11001110iiiiiiii
(R0+GBR) ^ imm → (R0+GBR) –
4
Test
result
1
Test
result
1
Test
result
3
Test
result
1
–
1
–
3
–
Rev. 2.00, 09/03, page 56 of 690