HD6417705 Datasheet, PDF (185/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

• USB interface (USB)
• Timer unit (TMU)
• 16-bit timer pulse unit (TPU)
• Watchdog timer (WDT)
• Bus state controller (BSC)
• User-debugging interface (UDI)
• Realtime clock (RTC)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the
interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value
of INTEVT or INTEVT2 as a branch offset.
A priority level (from 0 to 15) can be set for each module except UDI by writing to the interrupt
priority level setting registers A to H (IPRA to IPRH). The priority level of the UDI interrupt is 15
(fixed).
The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral
module interrupt handling.
6.4.6 Interrupt Exception Handling and Priority
There are five types of interrupt sources: NMI, IRQ, IRL, PINT, and on-chip peripheral modules.
The priority of each interrupt source is set within priority levels 0 to 16; level 16 is the highest and
level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt
request is ignored.
Tables 6.4 and 6.5 list the codes for the interrupt source and the interrupt event registers (INTEVT
and INTEVT2) and the order of interrupt priority.
Each interrupt source is assigned a unique code by INTEVT and INTEVT2. The start address of
the interrupt service routine is common for each interrupt source. This is why, for instance, the
value of INTEVT2 is used as an offset at the start of the interrupt service routine and branched to
in order to identify the interrupt source.
IRQ and PINT interrupts, and on-chip peripheral module interrupt priorities can be set freely
between 0 and 15 for each module by setting the interrupt priority level setting registers. A reset
assigns priority level 0 to IRQ, PINT, and on-chip peripheral module interrupts.
If the same priority level is assigned to two or more interrupt sources and interrupts from those
sources occur simultaneously, their priority order is the default priority order indicated at the right
in tables 6.4 and 6.5.
Rev. 2.00, 09/03, page 139 of 690