HD6417705 Datasheet, PDF (309/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

This LSI
External address bus External data bus
DMAC
External
memory
External device
with DACK
Data flow
DACK
DREQ
Figure 8.7 Data Flow in Single Address Mode
Two kinds of transfer are possible in single address mode: (1) transfer between an external
device with DACK and a memory-mapped external device, and (2) transfer between an
external device with DACK and external memory. In both cases, only the external request
signal (DREQ) is used for transfer requests.
Figures 8.8 shows example of DMA transfer timing in single address mode.
CKIO
A25 to A0
CSn
WE
D31 to D0
DACKn
Address output to external memory space
Select signal to external memory space
Write strobe signal to external memory space
Data output from external device with DACK
DACK signal (active-low) to external device with DACK
(a) External device with DACK → external memory space (ordinary memory)
CKIO
A25 to A0
CSn
RD
Address output to external memory space
Select signal to external memory space
Read strobe signal to external memory space
D31 to D0
DACKn
Data output from external memory space
DACK signal (active-low) to external device with DACK
(b) External memory space (ordinary memory) → external device with DACK
Figure 8.8 Example of DMA Transfer Timing in Single Address Mode
Rev. 2.00, 09/03, page 263 of 690