HD6417705 Datasheet, PDF (444/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

16.3.10 FIFO Control Register (SCFCR)
SCFCR is a 16-bit readable/writable register that resets the data count and sets the trigger data
number for the transmit and receive FIFO registers, and also contains a loopback test enable bit.
Bit
Initial
Bit
Name Value R/W
15
TSE
0
R/W
14
TCRST 0
R/W
13 to 11 
0
R
10
RSTRG2 0
R/W
9
RSTRG1 0
R/W
8
RSTRG0 0
R/W
Description
Transmit Data Stop Enable
Enables or disables the transmit data stop function.
This function is enabled only in asynchronous mode.
Since this function is not supported in clock synchronous
mode, clear this bit to 0 in clock synchronous mode.
0: Transmit data stop function disabled
1: Transmit data stop function enabled
Transmit Count Reset
Clears the transmit count to 0. This bit is valid only when
the transmit data stop function is used.
0: Transmit count reset disabled^*
1: Transmit count reset enabled (clearing to 0)
Note:* The transmit count is reset (clearing to 0) is
performed in power-on reset or manual reset.
Reserved
These bits are always read as 0. The write value should
always be 0.
RTS Output Active Trigger
The RTS signal goes high when the number of receive
data bytes in SCFRDR is equal to or greater than the
trigger set number shown in below.
000: 63
001: 1
010: 8
011: 16
100: 32
101: 48
110: 54
111: 60
Rev. 2.00, 09/03, page 398 of 690