HD6417705 Datasheet, PDF (205/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
24

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
23
IWRWS1 1
R/W Idle Cycles for Read-write in the Same Space
22
IWRWS0 1
R/W Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the space. The
target cycle is a read-write cycle of which continuous
accesses are for the same space.
00: Setting prohibited.
01: 2 idle cycles inserted
10: 3 idle cycles inserted
11: 5 idle cycles inserted
21

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
20
IWRRD1 1
R/W Idle Cycles for Read-read in Another Space
19
IWRRD0 1
R/W Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the space. The
target cycle is a read-read cycle of which continuous
accesses switch between different space.
00: 1 idle cycle inserted
01: 2 idle cycles inserted
10: 3 idle cycles inserted
11: 5 idle cycles inserted
18

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
17
IWRRS1 1
R/W Idle Cycles for Read-read in the Same Space
16
IWRRS0 1
R/W Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the space. The
target cycle is a read-read cycle of which continuous
accesses are for the same space.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Rev. 2.00, 09/03, page 159 of 690