HD6417705 Datasheet, PDF (144/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit
Name
Value R/W Description
31 to 17 —
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
16
LE
0
R/W Lock Enable (LE)
Controls cache lock mode.
0: Does not enter cache lock mode.
1: Enters cache lock mode.
15 to 10 —
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9
W3LOAD 0
R/W Way 3 Load (W3LOAD)
8
W3LOCK 0
R/W Way 3 Lock (W3LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W3LOAD
and W3LOCK in CCR2 are set to 1, the data is
always loaded into way 3. Under any other condition,
the prefetched data is loaded into the way to which
LRU points.
7 to 2
—
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
W2LOAD 0
R/W Way 2 Load (W2LOAD)
0
W2LOCK 0
R/W Way 2 Lock (W2LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W2LOAD
and W2LOCK in CCR2 are set to 1, the data is
always loaded into way 2. Under any other condition,
the prefetched data is loaded into the way to which
LRU points.
Note: W2LOAD and W3LOAD should not be set to 1 at the same time.
Rev. 2.00, 09/03, page 98 of 690