HD6417705 Datasheet, PDF (614/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

23.2 Input/Output Pins
Table 23.1 shows the pin configuration of the UDI.
Table 23.1 Pin Configuration
Pin Name
TCK^*
TMS^*
TRST^*
TDI^*
TDO
ASEMD0^*
Input/Output
Input
Input
Input
Input
Output
Input
Description
Serial Data Input/Output Clock Pin
Data is serially supplied to the UDI from the data input pin
(TDI), and output from the data output pin (TDO), in
synchronization with this clock.
Mode Select Input Pin
The state of the TAP control circuit is determined by changing
this signal in synchronization with TCK. The protocol is
supported to the JTAG standard (IEEE Std.1149.1).
Reset Input Pin
Input is accepted asynchronously with respect to TCK, and
when low, the UDI is reset. TRST must be held low for a
constant period when power is turned on regardless of using
the UDI function. As the same as the RESETP pin, the TRST
pin should be driven low at the power-on reset state and driven
high after the power-on reset state is released. This is different
from the JTAG standard.
See section 23.4.2, Reset Configuration, for more information.
Serial Data Input Pin
Data transfer to the UDI is executed by changing this signal in
synchronization with TCK.
Serial Data Output Pin
Data read from the UDI is executed by reading this pin in
synchronization with TCK. The data output timing depends on
the command type set in the SDIR. See section 23.3.2,
Instruction Register (SDIR), for more information.
ASE Mode Select Pin
If a low level is input at the ASEMD0 pin while the RESETP pin
is asserted, ASE mode is entered; if a high level is input, normal
mode is entered. In ASE mode, dedicated emulator function
can be used. The input level at the ASEMD0 pin should be held
for at least one cycle after RESETP negation. See section
23.4.2, Reset Configuration, for more information.
Rev. 2.00, 09/03, page 568 of 690