HD6417705 Datasheet, PDF (488/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit Bit Name
1
EP0iTR
0
EP0iTS
Initial
Value R/W
0
R/W
0
R/W
Description
EP0i Transfer Request
This bit is set if there is no valid transmit data in the FIFO
buffer when an IN token for endpoint 0 is received from
the host. A NACK handshake is returned to the host until
data is written to the FIFO buffer and packet transmission
is enabled.
EP0i Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 0 and an ACK handshake is returned.
18.3.2 Interrupt Flag Register 1 (IFR1)
IFR1, together with interrupt flag register 0 (IFR0), indicates interrupt status information required
by the application. When an interrupt source is generated, the corresponding bit is set to 1 and an
interrupt request is sent to the CPU according to the combination with interrupt enable register 1
(IER1). Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits.
Bit Bit Name
7 to 4 
3
VBUSMN
2
EP3TR
1
EP3TS
0
VBUS
Initial
Value R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
This is a status bit which monitors the state of the VBUS
pin. This bit reflects the state of the VBUS pin.
EP3 Transfer Request
This bit is set if there is no valid transmit data in the FIFO
buffer when an IN token for endpoint 3 is received from
the host. A NACK handshake is returned to the host until
data is written to the FIFO buffer and packet transmission
is enabled.
EP3 Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 3 and an ACK handshake is returned.
USB Disconnection Detection
When the function is connected to the USB bus or
disconnected from it, this bit is set to 1. The VBUS pin of
this module is used for detecting connection or
disconnection.
Rev. 2.00, 09/03, page 442 of 690