HD6417705 Datasheet, PDF (447/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

16.3.11 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit read-only register that indicates the number of data bytes stored in the transmit
FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR).
Bits 14 to 8 show the number of transmit data bytes in SCFTDR, and bits 6 to 0 show the number
of receive data bytes in SCFRDR.
Bit
Bit
Name
15

14 to 8 T6 to
T0
7

6 to 0
R6 to
R0
Initial
Value R/W Description
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
0
R
These bits show the number of untransmitted data
bytes in SCFTDR.
A value of H'00 means that there is no transmit data,
and a value of H'40 means that SCFTDR is full of
transmit data.
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
0
R
These bits show the number of receive data bytes in
SCFRDR.
A value of H'00 means that there is no receive data,
and a value of H'40 means that SCFRDR is full of
receive data.
16.3.12 Transmit Data Stop Register (SCTDSR)
SCTDSR is an 8-bit readable/writable register that sets the number of transmit data bytes.
SCTDSR is valid only when the TSE bit in the FIFO control register (SCFCR) is enabled.
Transmit operation is stopped when the number of data bytes set in SCTDSR is transmitted. The
setting value should be H'00 (one byte) to H'FF (256 bytes). This function is only enabled in
asynchronous mode.
SCTDSR is initialized to H'FF.
Rev. 2.00, 09/03, page 401 of 690