HD6417705 Datasheet, PDF (579/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

21.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has three
operating modes: single mode, multi mode, and scan mode. To avoid malfunction, switch
operating modes while the ADST bit of ADCSR is 0. Changing operating modes and channels and
setting the ADST bit can be performed simultaneously.
21.4.1 Single Mode
Single mode should be selected when only one A/D conversion on one channel is required.
1. A/D conversion of the selected channel starts when the ADST bit of ADCSR is set to 1 by
software.
2. When conversion ends, the conversion results are transmitted to the A/D data register that
corresponds to the channel.
3. When conversion ends, the ADF bit of ADCSR is set to 1. If the ADIE bit is also set to 1, an
ADI interrupt is requested at this time.
4. The ADST bit holds 1 during A/D conversion. When A/D conversion is completed, the ADST
bit is cleared to 0 and the A/D converter becomes idle. When the ADST bit is cleared to 0
during A/D conversion, the conversion is halted and the A/D converter becomes idle.
To clear the ADF flag to 0, first read ADF, then write 0 to ADF.
21.4.2 Multi Mode
Multi mode should be selected when performing A/D conversions on one or more channels.
1. When the ADST bit is set to 1 by software, A/D conversion starts with the smaller number of
the analog input channel in the group (for instance, AN0, and AN1 to AN3).
2. When conversion of each channel ends, the conversion results are transmitted to the A/D data
register that corresponds to the channel.
3. When conversion of all selected channels ends, the ADF bit of ADCSR is set to 1. If the
ADIE bit is also set to 1, an ADI interrupt is requested at this time.
4. When A/D conversion is completed, the ADST bit is cleared to 0 and the A/D converter
becomes idle. When the ADST bit is cleared to 0 during A/D conversion, the conversion is
halted and the A/D converter becomes idle.
To clear the ADF flag to 0, first read ADF, then write 0 to ADF.
Rev. 2.00, 09/03, page 533 of 690