HD6417705 Datasheet, PDF (343/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

11.3.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in the power-
down mode.
Bit
Bit Name Initial Value R/W Description
7
MSTP10 0
R/W Module Stop Bit 10
When the MSTP10 bit is set to 1, the clock supply to
the UDI is halted.
0: UDI runs
1: Clock supply to UDI is halted
6
MSTP9 0
R/W Module Stop Bit 9
When the MSTP9 bit is set to 1, the clock supply to
the UBC is halted.
0: UBC runs
1: Clock supply to UBC is halted
5
MSTP8 0
R/W Module Stop Bit 8
When the MSTP8 bit is set to 1, the clock supply to
the DMAC is halted.
0: DMAC runs
1: Clock supply to DMAC is halted
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
MSTP6 0
R/W Module Stop Bit 6
When the MSTP6 bit is set to 1, the clock supply to
the TLB is halted.
0: TLB runs
1: Clock supply to TLB is halted
2
MSTP5 0
R/W Module Stop Bit 5
When the MSTP5 bit is set to 1, the clock supply to
cache memory is halted.
0: Cache memory runs
1: Clock supply to cache memory is halted
Rev. 2.00, 09/03, page 297 of 690