HD6417705 Datasheet, PDF (219/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CS3WCR
Bit
Bit Name
31 to 15 
Initial
Value R/W
0
R
14
TRP1 0
R/W
13
TRP0 0
R/W
12

0
R
11
TRCD1 0
R/W
10
TRCD0 1
R/W
9

0
R
8
A3CL1 1
R/W
7
A3CL0 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Cycles from Auto-precharge/PRE Command to
ACTV Command
Specify the number of minimum cycles from the start of auto-
precharge or issuing of PRE command to the issuing of ACTV
command for the same bank. The setting for areas 2 and 3 is
common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Reserved
This bit is always read as 0. The write value should always be
0.
Number of Cycles from ACTV Command to
READ(A)/WRIT(A) Command
Specify the number of minimum cycles from issuing ACTV
command to issuing READ(A)/WRIT(A) command. The
setting for areas 2 and 3 is common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Reserved
This bit is always read as 0. The write value should always be
0.
CAS Latency for Area 3
Specify the CAS latency for area 3.
00: Setting prohibited.
01: 2 cycles
10: 3 cycles
11: Setting prohibited
Rev. 2.00, 09/03, page 173 of 690