HD6417705 Datasheet, PDF (405/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
7
6 to 4
3 to 0
Bit Name
ENB
Initial Value R/W
0
R/W


R/W


R/W
Description
Second Alarm Enable
Specifies whether to compare RSECCNT with
RSECAR to generate a second alarm.
0: Not compared
1: Compared
10-unit of second alarm setting in the BCD-code.
The range that can be set is 0 to 5 (decimal).
1-unit of second alarm setting in the BCD-code.
The range that can be set is 0 to 9 (decimal).
15.3.10 Minute Alarm Register (RMINAR)
The minute alarm register (RMINAR) is an 8-bit readable/writable register, and an alarm register
corresponding to the minute counter RMINCNT. When the ENB bit is set to 1, a comparison with
the RMINCNT value is performed. For alarm registers RSECAR, RMINAR, RHRAR, RWKAR,
RDAYAR, and RMONAR, a comparison with the corresponding counter value is performed for
those whose ENB bit is set to 1, and for RCR3, a comparison is performed when the YAEN bit is
set to 1. If all of those match, an RTC alarm interrupt is generated.
The range of minute alarm that can be set is 00 to 59 (decimal). Errant operation will result if any
other value is set.
The ENB bit in RMINAR is initialized by a power-on reset, and it is not initialized by manual
reset and standby mode. The remaining RMINAR fields are not initialized by a power-on reset or
manual reset, or in standby mode.
Bit
7
6 to 4
3 to 0
Bit Name
ENB
Initial Value R/W
0
R/W


R/W


R/W
Description
Minute Alarm Enable
Specifies whether to compare RMINCNT with
RMINAR to generate a second alarm.
0: Not compared
1: Compared
10-unit of minute alarm setting in the BCD-code.
The range that can be set is 0 to 5 (decimal).
1-unit of minute alarm setting in the BCD-code.
The range that can be set is 0 to 9 (decimal).
Rev. 2.00, 09/03, page 359 of 690