HD6417705 Datasheet, PDF (33/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figures
Section 1 Overview
Figure 1.1 Block Diagram of SH7705 ........................................................................................6
Figure 1.2 Pin Assignment (FP-208C) .......................................................................................7
Figure 1.3 Pin Assignment (TBP-208A).....................................................................................8
Section 2 CPU
Figure 2.1 Processing State Transitions.................................................................................... 26
Figure 2.2 Logical Address to External Memory Space Mapping ............................................. 29
Figure 2.3 Register Configuration in Each Processing Mode .................................................... 31
Figure 2.4 General Registers.................................................................................................... 33
Figure 2.5 System Registers and Program Counter ................................................................... 34
Figure 2.6 Control Register Configuration ............................................................................... 37
Figure 2.7 Data Format on Memory (Big Endian Mode)........................................................... 38
Figure 2.8 Data Format on Memory (Little Endian Mode)........................................................ 39
Section 3 Memory Management Unit (MMU)
Figure 3.1 MMU Functions ..................................................................................................... 66
Figure 3.2 Virtual Address Space (MMUCR.AT = 1)............................................................... 68
Figure 3.3 Virtual Address Space (MMUCR.AT = 0)............................................................... 69
Figure 3.4 P4 Area .................................................................................................................. 69
Figure 3.5 External Memory Space .......................................................................................... 70
Figure 3.6 Overall Configuration of the TLB ........................................................................... 75
Figure 3.7 Virtual Address and TLB Structure ......................................................................... 76
Figure 3.8 TLB Indexing (IX = 1)............................................................................................ 77
Figure 3.9 TLB Indexing (IX = 0)............................................................................................ 78
Figure 3.10 Objects of Address Comparison ............................................................................ 79
Figure 3.11 Operation of LDTLB Instruction ........................................................................... 82
Figure 3.12 Synonym Problem (32-kbyte Cache) ..................................................................... 84
Figure 3.13 MMU Exception Generation Flowchart ................................................................. 89
Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access............................ 91
Section 4 Cache
Figure 4.1 Cache Structure (32-kbyte Mode)............................................................................ 94
Figure 4.2 Cache Search Scheme ........................................................................................... 101
Figure 4.3 Write-Back Buffer Configuration .......................................................................... 103
Figure 4.4 Specifying Address and Data for Memory-Mapped Cache Access
(32-kbyte Mode).................................................................................................... 106
Section 5 Exception Handling
Figure 5.1 Register Bit Configuration .................................................................................... 110
Section 6 Interrupt Controller (INTC)
Figure 6.1 Block Diagram of INTC........................................................................................ 126
Rev. 2.00, 09/03, page xxxiii of xlvi