HD6417705 Datasheet, PDF (576/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

21.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion. Table 21.2 indicates the pairings of analog input channels and A/D data
registers that store the results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into bits 15 to 6 in the
A/D data register corresponding to the selected channel. Bits 5 to 0 of an A/D data register are
reserved bits that are always read as 0.
The A/D data registers are initialized to H'0000.
Table 21.2 Analog Input Channels and A/D Data Registers
Analog Input Channel
AN0
AN1
AN2
AN3
A/D Data Register that Store Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
21.3.2 A/D Control/Status Registers (ADCSR)
ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter.
Bit
Initial
Bit Name Value R/W Description
15
ADF
0
R/(W)^* A/D End Flag
Indicates the end of A/D conversion.
[Setting conditions]
Single mode: A/D conversion ends
Multi mode: A/D conversion ends cycling through the
selected channels
Scan mode: A/D conversion ends cycling through the
selected channels
[Clearing conditions]
(1) Reading ADF while ADF = 1, then writing 0 to ADF
(2) DMAC is activated by ADI interrupt and ADDR is
read
Note: * Clear this bit by writing 0. Writing 1 is ignored.
Rev. 2.00, 09/03, page 530 of 690