HD6417705 Datasheet, PDF (475/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

d. Receive Data Sampling Timing and Receive Margin:
As an example, when the sampling rate is 1/16, the SCIF operates on a base clock with a
frequency of 8 times the transfer rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the fourth base clock pulse.
The receive margin can therefore be expressed as shown in equation (1).
M=
0.5 −
1
2N
− (L − 0.5)F −
D − 0.5 _{(1 + F) × 100% .......................... (1)}
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ........................................... (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 2.00, 09/03, page 429 of 690