HD6417705 Datasheet, PDF (198/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Name
CKE
AH
WAIT
BREQ
BACK
MD3, MD4
MD5
I/O
Function
O
Connects to CKE pin when SDRAM is connected.
O
Holds the address in address/data multiplex I/O mode.
I
External wait input
I
Bus request input
O
Bus acknowledge output
I
Area 0 bus width (8/16/32 bits)
I
Specifies endian
0: Big endian
1: Little endian
7.3 Area Overview
In the architecture of this LSI, both logical spaces and physical spaces have 32-bit address spaces.
The cache access method is shown by the upper 3 bits. For details see section 4, Cache. The
remaining 29 bits are used for division of the space into eight areas. The BSC performs control for
this 29-bit space.
As listed in table 7.2, this LSI can be connected directly to eight areas of memory, and it outputs
chip select signals (CS0, CS2 to CS4, CS5A, CS5B, CS6A, and CS6B) for each of them. CS0 is
asserted during area 0 access; CS5B is asserted during area 5B access. When an SDRAM is
connected to area 2 or area 3, RASU, RASL, CASU, CASL, DQMUU, DQMUL, DQMLU, and
DQMLL are asserted.
7.3.1 Address Map
The external address space has a capacity of 384 Mbytes and is used by dividing 8 partial spaces.
The kind of memory to be connected and the data bus width are specified in each partial space.
The address map for the external address space is listed below.
Table 7.2 Physical Address Space Map
Area
Area 0
Memory to be
Connected
Normal memory^*1,
Burst ROM
Physical Address
Access
Capacity Size
H'00000000
to H'03FFFFFF 64 Mbytes _{8, 16, 32}*²
H'00000000
to H'03FFFFFF Shadow (n: 1 to 6)
+H'20000000×n +H'20000000×n
Rev. 2.00, 09/03, page 152 of 690