HD6417705 Datasheet, PDF (196/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

• Bus arbitration
 Shares all of the resources with other CPU and outputs the bus enable after receiving the
bus request from external devices.
7.1.2 Block Diagram
BSC functional block diagram is shown in figure 7.1.
BSC
Output
signal drive
controller
Wait between
access cycles
controller
Internal
Internal
address bus data bus
CMNCR
CSnBCR*
CS0, CS2, CS3, CS4,
CS5A, CS5B, CS6A, CS6B
Area
controller
WAIT
Wait
controller
CSnWCR*
BS, RD, RD/WR, WE3 to WE0,
RASU, RASL, CASU, CASL,
AH, CKE, DQMUU, DQMUL,
DQMLU, DQMLL
Memory
controller
Refresh
controller
SDCR
RTCSR
RTCNT
Comparator
A25 to 0
D31 to 0
Address/data
controller
RTCOR
Note: * CSnBCR, CSnWCR : n = 0, 2, 3, 4, 5A, 5B, 6A, 6B
Legend:
CSnBCR : Area n bus control register
CSnWCR : Area n wait control register
SDCR
: SDRAM control register
RTCSR : Refresh timer control/status register
RTCNT : Refresh timer counter
RTCOR : Refresh timer constant register
Figure 7.1 BSC Functional Block Diagram
Rev. 2.00, 09/03, page 150 of 690