HD6417705 Datasheet, PDF (345/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
2
MSTP32 0
R/W Module Stop Bit 32
When the MSTP32 bit is set to 1, the clock supply to
the IrDA is halted.
0: IrDA runs
1: Clock supply to IrDA is halted
1
MSTP31 0
R/W Module Stop Bit 31
When the MSTP31 bit is set to 1, the clock supply to
the SCIF2 is halted.
0: SCIF2 runs
1: Clock supply to SCIF2 is halted
0
MSTP30 0
R/W Module Stop Bit 30
When the MSTP30 bit is set to 1, the clock supply to
the SCIF0 is halted.
0: SCIF0 runs
1: Clock supply to SCIF0 is halted
11.4 Sleep Mode
11.4.1 Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral
modules continue to run in sleep mode and the clock continues to be output to the CKIO pin.
In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low.
11.4.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, and on-chip peripheral module) or
reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save
SPC and SSR to the stack before executing the SLEEP instruction.
Canceling with an Interrupt: When an NMI, IRQ, IRL, PINT, or on-chip peripheral module
interrupt occurs, sleep mode is canceled and interrupt exception processing is executed. A code
indicating the interrupt source is set in INTEVT and INTEVT2.
Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset.
Rev. 2.00, 09/03, page 299 of 690