HD6417705 Datasheet, PDF (422/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

There are six interrupt sourcestransmit-data-stop, transmit-FIFO-data-empty, receive-FIFO-
data-full, receive-error (framing/parity error), break-receive, and receive-data-ready interrupts.
• Two interrupt sources in clock synchronous mode
There are two interrupt sourcestransmit-FIFO-data-empty and receive-FIFO-data-full
interrupts.
• The DMA controller (DMAC) can be activated to execute a data transfer in the event of a
transmit-FIFO-data-empty, transmit-data-stop, or receive-FIFO-data-full interrupt. The DMAC
requests of transmit-FIFO-data-empty and transmit-data-stop interrupts are the same.
• On-chip modem control functions (CTS and RTS)
• On-chip transmit-data-stop functions (only in asynchronous mode)
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
consumption.
• The amount of data in the transmit/receive FIFO registers and the number of receive errors in
the receive data in the receive FIFO register can be ascertained.
Rev. 2.00, 09/03, page 376 of 690