HD6417705 Datasheet, PDF (282/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

1. 16-byte transition because of a cache miss
2. During copyback operation for the cache
3. Between the read and write cycles of a TAS instruction
4. Multiple bus cycles generated when data bus width is smaller than the access size (For
example, between bus cycles when longword access is made to memory with a data bus width
of 8 bits.)
5. 16-byte transfer by the DMAC
If self-refresh mode is specified for the SDRAM, the master device cannot release the bus. If the
master clock stops because a transition is underway to standby mode or the frequency is changed,
or if this LSI is being reset, the master device cannot release the bus. To prevent the slave from
issuing bus requests in such a case, the slave must be put into the sleep state so that no slave
access cycles are generated.
The refresh request and bus request are accepted during the DMA burst transfer.
Bus mastership is maintained until a new bus request is received. Bus mastership is released
immediately after the completion of the bus cycle in progress when an external bus request
(BREQ) is asserted (low level) and a bus acknowledge signal (BACK) is asserted (low level). Bus
use is resumed when a negation (high level) of BREQ, which shows that the slave has released the
bus, has been received.
SDRAM issues all bank pre-charge commands (PALLs) when active banks exist and releases the
bus after completion of a PALL command.
The bus release sequence is as follows. The address bus and data bus are placed in a high-
impedance state synchronized with the rising edge of CKIO. The bus mastership enable signal is
asserted 0.5 cycles after the above timing, synchronized with the falling edge of CKIO. Bus
control signals (BS, CSn, RASU, RASL, CASU, CASL, DQMxx, WEn, RD, and RD/WR) are
made to the high-impedance states at the subsequent rising edge of CKIO. Bus request signals are
sampled at the falling edge of CKIO. The sequence for re-claiming bus mastership from a slave is
described below. After detecting the negation of BREQ at the falling edge of CKIO, the bus
enable signal is negated at the subsequent falling edge of the clock. The address and data signals
are driven at the subsequent rising edge of CKIO. Figure 7.34 shows the bus arbitration timing.
Rev. 2.00, 09/03, page 236 of 690