HD6417705 Datasheet, PDF (179/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

6.3.6 Interrupt Request Register 0 (IRR0)
IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5
and PINT0 to PINT15.
Bit
7
6
5 to 0
Bit Name
PINT0R
PINT1R
IRQ5R to
IRQ0R
Initial Value R/W
0
R
0
R
0
R/W
Description
PINT0 to PINT7 Interrupt Request
Indicates whether interrupt requests are input to
PINT0 to PINT7 pins.
0: Interrupt requests are not input to PINT0 to
PINT7 pins
1: Interrupt requests are input to PINT0 to PINT7
pins
PINT8 to PINT15 Interrupt Request
Indicates whether interrupt requests are input to
PINT8 to PINT15 pins.
0: Interrupt requests are not input to PINT8 to
PINT15 pins
1: Interrupt requests are input to PINT8 to
PINT15 pins
IRQn Interrupt Request
Indicates whether there is interrupt request input
to the IRQn pin. When edge-detection mode is
set for IRQn, an interrupt request is cleared by
writing 0 to the IRQnR bit after reading IRQnR =
1.
When level-detection mode is set for IRQn, these
bits indicate whether an interrupt request is input.
The interrupt request is set/cleared by only 1/0
input to the IRQn pin.
IRQnR
0: No interrupt request input to IRQn pin
1: Interrupt request input to IRQn pin
[Legend] n = 0 to 5
Rev. 2.00, 09/03, page 133 of 690