HD6417705 Datasheet, PDF (263/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8.6 Single Write
A write access ends in one cycle when data is written in non-cacheable region and the data bus
width is larger than or equal to access size. This is called single write. Figure 7.19 shows the basic
timing chart for single write.
Tr
Tc1 Trwl
Tap
CKIO
A25 to A0
A12/A11^*1
CSn
RASU/L
CASU/L
RD/WR
DQMxx^*2
D31 to D0
BS
DACKn^*3
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. xx is UU, UL, LU, or LL.
3. The waveform for DACKn is when active low is specified.
Figure 7.19 Basic Timing for Single Write (Auto Precharge)
Rev. 2.00, 09/03, page 217 of 690