HD6417705 Datasheet, PDF (446/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name
2 TFRST
1 RFRST
0 LOOP
Initial
Value R/W Description
0
R/W Transmit FIFO Data Register Reset
Invalidates the transmit data in the transmit FIFO data
register and resets it to the empty state.
0: Reset operation disabled^*
1: Reset operation enabled
Note:* A reset operation is performed in the event of a
power-on reset or manual reset.
0
R/W Receive FIFO Data Register Reset
Invalidates the receive data in the receive FIFO data
register and resets it to the empty state.
0: Reset operation disabled^*
1: Reset operation enabled
Note:* A reset operation is performed in the event of a
power-on reset or manual reset.
0
R/W Loopback Test
Internally connects the transmit output pin (TxD) and
receive input pin (RxD), and RTS pin and CTS pin, enabling
loopback testing.
0: Loopback test disabled
1: Loopback test enabled
Rev. 2.00, 09/03, page 400 of 690