HD6417705 Datasheet, PDF (342/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

11.3.1 Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode.
Bit
Bit Name Initial Value R/W Description
7
STBY
0
R/W Standby
Specifies transition to software standby mode.
0: Executing SLEEP instruction puts chip into sleep
mode
1: Executing SLEEP instruction puts chip into
software standby mode
6, 5

0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
4
STBXTL 0
R/W Standby Crystal
Specifies stop/start of the crystal oscillator in
standby mode.
0: Crystal oscillator stops in standby mode.
1: Crystal oscillator continues operation in standby
mode.
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
MSTP2 0
R/W Module Stop 2
Specifies halting the clock supply to the TMU when
the MSTP2 bit has been set to 1.
0: TMU runs
1: Clock supply to TMU halted
1
MSTP1 0
R/W Module Stop 1
Specifies halting the clock supply to the RTC when
the MSTP1 bit has been set to 1.
0: RTC runs
1: Clock supply to RTC halted
0

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 296 of 690