HD6417705 Datasheet, PDF (468/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

c. Serial Data Reception
Figure 16.15 shows sample flowcharts for serial reception.
Start of reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR
[1]
Set RE bit in SCSCR
When using receive FIFO data interrupt, [2]
set RIE bit to 1
RDF =1?
No
Yes
Read receive trigger number of receive
data bytes from SCFRDR
[3]
Clear RE bit in SCSCR to 0
[4]
[1] Set the receive trigger number
in SCFCR.
[2] Reception is started when the
RE bit in SCSCR is set to 1.
[3] Read receive data while the
RDF bit is 1.
[4] After the end of reception, clear
the RE bit to 0.
End of reception
Figure 16.15 Sample Serial Reception Flowchart (1)
(First Reception after Initialization)
Rev. 2.00, 09/03, page 422 of 690