HD6417705 Datasheet, PDF (64/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Classification Symbol
I/O
Operating mode MD6 to MD0 I
control
System control RESETP
I
RESETM
I
STATUS1,
O
STATUS0
BREQ
I
BACK
O
Interrupts
CA
I
NMI
I
IRQ5 to IRQ0 I
IRL3 to IRL0 I
PINT15 to
I
PINT0
Address bus
A25 to A0
O
Data bus
D31 to D0
I/O
Name
Function
Mode set
Sets the operating mode. Do not
change values on these pins
during operation.
MD2 to MD0 set the clock mode,
MD3 and MD4 set the bus-width
mode of area 0 and MD5 sets the
endian. MD6 pin should be
connected to VssQ.
Power-on reset When low, the system enters the
power-on reset state.
Manual reset When low, the system enters the
manual reset state.
Status output Indicates the operating state.
Bus request
Low when an external device
requests the release of the bus
mastership.
Bus request
acknowledge
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which
has output the BREQ signal that it
has acquired the bus.
Chip active
High in normal operation, and low
in hardware standby mode.
Non-maskable Non-maskable interrupt request
interrupt
pin. Fix to high level when not in
use.
Interrupt
requests 5 to 0
Maskable interrupt request pin.
Selectable as level input or edge
input. The rising edge or falling
edge is selectable as the detection
edge. The low level or high level is
selectable as the detection level.
Interrupt
Maskable interrupt request pin.
requests 3 to 0 _{Input a coded interrupt level.}
Interrupt
PINT interrupt request pin.
requests 15 to 0
Address bus Outputs addresses.
Data bus
32-bit bidirectional data bus.
Rev. 2.00, 09/03, page 18 of 690