HD6417705 Datasheet, PDF (189/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Interrupt Source
Interrupt Code^*1
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
Priority
within IPR Default
Setting Unit Priority
SCIF2 ERI2
RXI2
TXI2
ADC ADI
USB USI0
USI1
TPU0 TPI0
TPU1 TPI1
TPU2 TPI2
TPU3 TPI3
TMU0 TUNI0
TMU1
TMU2
RTC
WDT
TUNI1
TUNI2
TICPI2
ATI
PRI
CUI
ITI
REF RCMI
H'900^*3
H'920^*3
H'960^*3
H'980^*3
H'A20^*3
H'A40^*3
H'C00^*3
H'C20^*3
H'C80^*3
H'CA0^*3
H'400^*2
H'420^*2
H'440^*2
H'460^*2
H'480^*2
H'4A0^*2
H'4C0^*2
H'560^*2
H'580^*2
0 to 15 (0) IPRE (7 to 4) High
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
Low
IPRE (3 to 0) —
IPRF (7 to 4) High
Low
IPRG (15 to —
12)
IPRG (11 to —
8)
IPRH (15 to —
12)
IPRH (11 to —
8)
IPRA (15 to —
12)
IPRA (11 to 8)—
IPRA (7 to 4) High
Low
IPRA (3 to 0) High
0 to 15 (0)
0 to 15 (0)
Low
IPRB (15 to —
12)
IPRB (11 to 8)—
High
Low
Notes: 1. The INTEVT2 code.
2. The same code as INTEVT2 is set in INTEVT.
3. The code indicating an interrupt level (H'200 to H'3C0 shown in table 6.6) is set in
INTEVT.
Rev. 2.00, 09/03, page 143 of 690