HD6417705 Datasheet, PDF (244/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.8 SDRAM Interface
7.8.1 SDRAM Direct Connection
Since synchronous DRAM can be selected by the CS signal, physical space areas 2 and 3 can be
connected using RAS and other control signals in common. If the TYPE[2:0] bits in CSnBCR (n =
2 or 3) are set to 100, the synchronous DRAM interface can be selected. Do not set this value to
CSnBCR unless n = 2 or 3, otherwise the operation of this LSI is not guaranteed.
The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address,
8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in
read and write command cycles. The control signals for direct connection of SDRAM are RASU,
RASL, CASU, CASL, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3.
All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are
valid when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus
width of the area that is connected to SDRAM can be set to 32 or 16 bits.
Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as
the SDRAM operating mode.
Commands for SDRAM can be specified by RASU, RASL, CASU, CASL, RD/WR, and specific
address signals. These commands are shown below.
• NOP
• Auto-refresh (REF)
• Self-refresh (SELF)
• All banks pre-charge (PALL)
• Specified bank pre-charge (PRE)
• Bank active (ACTV)
• Read (READ)
• Read with pre-charge (READA)
• Write (WRIT)
• Write with pre-charge (WRITA)
• Write mode register (MRS)
The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. For the
relationship between DQMxx and the byte to be accessed, refer to section 7.5, Endian/Access Size
and Data Alignment.
Figures 7.14 and 7.15 show examples of the connection of SDRAM with the LSI.
Rev. 2.00, 09/03, page 198 of 690