HD6417705 Datasheet, PDF (139/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 4 Cache
4.1 Features
• Capacity: 16 or 32 kbytes
• Structure: Instructions/data mixed, 4-way set associative
• Locking: Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 256 entries/way in 16-kbyte mode or 512 entries/way in 32-kbyte mode
• Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0
Group 1 (P0, P3, and U0 areas)
Group 2 (P1 area)
• Replacement method: Least-recently used (LRU) algorithm
Note: After power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way).
4.1.1 Cache Structure
The cache mixes instructions and data and uses a 4-way set associative system. It is composed of
four ways (banks), and each of which is divided into an address section and a data section. Note
that the following sections will be described for the 32-kbyte mode as an example. For other cache
size modes, change the number of entries and size/way according to table 4.1. Each of the address
and data sections is divided into 512 entries. The entry data is called a line. Each line consists of
16 bytes (4 bytes × 4). The data capacity per way is 8 kbytes (16 bytes × 512 entries) in the cache
as a whole (4 ways). The cache capacity is 32 kbytes as a whole. Figure 4.1 shows the cache
structure.
Table 4.1 Number of Entries and Size/Way in Each Cache Size
Cache Size
16 kbytes
32 kbytes
Number of Entries
256
512
Size/Way
4 kbytes
8 kbytes
CACH000S_000020020300
Rev. 2.00, 09/03, page 93 of 690