HD6417705 Datasheet, PDF (272/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
Tp
Tpw
Trr
Trc
Trc
Trc
A25 to A0
A12/A11^*1
CSn
RASU/L
CASU/L
RD/WR
DQMxx^*2
D31 to D0
Hi-Z
BS
DACKn^*3
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. xx is UU, UL, LU, or LL.
3. The waveform for DACKn is when active low is specified.
Figure 7.26 Auto-Refresh Timing
2. Self-refreshing
Self-refresh mode in which the refresh timing and refresh addresses are generated within the
synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the
RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp
cycle after the completion of the pre-charging bank. A SELF command is then issued after
inserting idle cycles of which number is specified by the TRP[1:0] bits in CSnWSR.
Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is
cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command
issuance is disabled for the number of cycles specified by the TRC[1:0] bits in CSnWCR. Self-
refresh timing is shown in figure 7.27. Settings must be made so that self-refresh clearing and
data retention are performed correctly, and auto-refreshing is performed at the correct
intervals. When self-refreshing is activated from the state in which auto-refreshing is set, auto-
refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-
refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-
refreshing takes time, this time should be taken into consideration when setting the initial value
of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to
be started immediately.
Rev. 2.00, 09/03, page 226 of 690