HD6417705 Datasheet, PDF (507/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.4.4 EP1 Bulk-Out Transfer (Dual FIFOs)
USB function
OUT token reception
Application
Space
in EP1 FIFO?
Yes
No
NACK
Data reception from host
ACK
Set EP1 FIFO full status
(IFR0.EP1 FULL = 1)
Interrupt request
Read EP1 receive data
size register (EPSZ1)
Read data from EP1
data register (EPDR1)
Write 1 to EP1 read
complete bit
(TRG.EP1 RDFN = 1)
Both
EP1 FIFOs empty?
No Interrupt request
Yes
Clear EP1 FIFO full status
(IFR0.EP1 FULL = 0)
Figure 18.10 EP1 Bulk-Out Transfer Operation
EP1 has two 64-byte FIFOs, but the user can receive data and read receive data without being
aware of this dual-FIFO configuration.
When one FIFO is full after reception is completed, the EP1FULL bit in IFR0 is set. After the first
receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and
so the next packet can be received immediately. When both FIFOs are full, NACK is returned to
the host automatically. When reading of the receive data is completed following data reception, 1
is written to the EP1RDFN bit in TRG. This operation empties the FIFO that has just been read,
and makes it ready to receive the next packet.
Rev. 2.00, 09/03, page 461 of 690