HD6417705 Datasheet, PDF (625/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

23.4.2 Reset Configuration
Table 23.4 Reset Configuration
ASEMD0^*1
H
RESETP
L
TRST
L
H
Chip State
Normal reset and UDI reset^*4
Normal reset^*4
H
L
UDI reset only
H
Normal operation
L
L
L
Reset hold^*2
H
In ASE user mode^*3: Normal reset
In ASE break mode^*3: RESETP assert is
masked
H
L
UDI reset only
H
Normal operation
Notes: 1. Performs normal mode and ASE mode settings
ASEMD0 = H, normal mode
ASEMD0 = L, ASE mode
2. In ASE mode, reset hold is enabled by driving the RESETP and TRST pins low for a
constant cycle. In this state, the CPU does not start up, even if RESETP is driven high.
When TRST is driven high, UDI operation is enabled, but the CPU does not start up.
The reset hold state is canceled by the following:
• Another RESETP assert (power-on reset)
• TRST reassert
3. ASE mode is classified into two modes; ASE break mode to execute the firm program
of an emulator and ASE user mode to execute the user program.
4. Make sure the TRST pin is low when the power is turned on.
23.4.3 TDO Output Timing
The timing of data output from the TDO is switched by the command type set in the SDIR. The
timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,
SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.
When the UDI commands (UDI reset negate, UDI reset assert, and UDI interrupt) are set, TDO is
output at the TCK rising edge earlier than the JTAG standard by a half cycle.
Rev. 2.00, 09/03, page 579 of 690