HD6417705 Datasheet, PDF (470/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

d. Simultaneous Serial Data Transmission and Reception
Figure 16.16 shows sample flowcharts for simultaneous serial transmission and reception.
Start of simultaneous
transmission/reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR
[1]
Write remaining transmit data to SCFTDR _[2]
Read TDFE and RDF bits in SCSSR
TDFE =1?
RDF =1?
No
Yes
Write 0 to TDFE and RDF bits in
SCSSR after reading 1 from them
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data interrupt,
set TIE bit to 1
[3]
When using receive FIFO data interrupt,
set RIE bit to 1
[1] Set the receive trigger number
in SCFCR.
[2] Write the remaining transmit data
to SCFTDR, and if there is receive
data in the FIFO, read receive data
until there is less than the receive
trigger setting number, read the
TDFE and RDF bits in SCSSR, and
if 1, clear to 0.
[3] Transmission/reception is started
when the TE and RE bits in SCSCR
are set to 1. The TE and RE bits
must be set simultaneously.
[4] After the end of transmission/reception,
clear the TE and RE bits to 0.
TDFE =1?
RDF =1?
No
Yes
Read receive trigger number of receive
data bytes from SCFRDR
Clear TE and RE bits in SCSCR to 0 [4]
End of
transmission/reception
Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1)
(First Transfer after Initialization)
Rev. 2.00, 09/03, page 424 of 690