HD6417705 Datasheet, PDF (736/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

SDID ................................................ 577
SDID/SDIDH..................... 594, 613, 621
SDIDL ............................... 594, 613, 621
SDIR...........................569, 594, 613, 621
SDMR2.......................229, 587, 601, 615
SDMR3.......................230, 587, 601, 615
STBCR .......................296, 588, 603, 616
STBCR2 .....................297, 588, 603, 616
STBCR3 .....................298, 588, 603, 616
TCNT (TMU) .............317, 589, 603, 616
TCNT (TPU)...............341, 589, 605, 617
TCOR .........................317, 589, 603, 616
TCPR..........................317, 589, 604, 616
TCR (TMU)................313, 589, 603, 616
TCR (TPU) .................334, 589, 605, 617
TEA................................... 586, 597, 614
TGR............................341, 589, 605, 617
TIER...........................339, 589, 605, 617
TIOR ..........................338, 589, 605, 617
TMDR ........................337, 589, 605, 617
TRA................................... 586, 596, 614
TRG............................448, 592, 609, 619
TSR ............................340, 589, 605, 617
TSTR (TMU) ..............312, 589, 603, 616
TSTR (TPU) ...............341, 589, 605, 617
TTB................................... 586, 595, 614
UCLKCR....................281, 588, 603, 616
WTCNT......................286, 588, 603, 616
WTCSR ......................287, 588, 603, 616
XVERCR....................453, 592, 609, 620
Reset State .............................................. 25
Round-Robin mode ............................... 258
RTC crystal oscillator circuit................. 372
Save Program Counter (SPC) .................. 36
Save Status Register (SSR)...................... 36
Scan mode ............................................ 534
SDRAM interface.................................. 198
Sequential break.................................... 559
Serial communication interface with FIFO
............................................................. 375
Setup stage............................................ 456
Shadow space........................................ 155
Signal-Source impedance ...................... 538
Single Address mode............................. 262
Single mode .......................................... 533
Single Virtual Memory Mode .................. 71
Sleep mode ........................................... 299
Software standby mode.......................... 300
Stall operations ..................................... 465
Status Register (SR) ................................ 35
Status stage ........................................... 459
Synonym problem ................................... 83
System Registers ..................................... 29
T Bit ....................................................... 40
TAP controller ...................................... 578
Timer Unit ............................................ 309
TRAPA Exception Register................... 110
USB function module............................ 437
USB standard commands....................... 464
User break controller ............................. 541
User break exception processing............ 555
Vector Base Register (VBR)................... 37
Virtual Address Space ............................. 67
Watchdog timer..................................... 285
Watchdog timer mode ........................... 291
Rev. 2.00, 09/03, page 690 of 690