HD6417705 Datasheet, PDF (375/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises four 16-bit timer channels.
14.1 Features
• Maximum 4-pulse output
A total of 16 timer general registers (TGRA to TGRD × 4 ch.) are provided (four each for
channels). TGRA can be set as an output compare register.
TGRB, TGRC, and TGRD for each channel can also be used as timer counter clearing
registers. TGRC and TGRD can also be used as buffer registers.
• Selection of four counter input clocks for channels 0 to 3
• The following operations can be set for each channel:
Waveform output at compare match: Selection of 0, 1, or toggle output
Counter clear operation: Counter clearing possible by compare match
PWM mode: Any PWM output duty cycle can be set
Maximum of 4-phase PWM output possible
• Buffer operation settable for each channel
Automatic rewriting of output compare register possible
• An interrupt request for each channel
Compare match and overflow interrupt requests can be enabled or disabled for each source
independently
TIMTPU8A_000020020100
Rev. 2.00, 09/03, page 329 of 690