HD6417705 Datasheet, PDF (204/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
CSnBCR is a 32-bit readable/writable register that specifies the function of each area, the number
of idle cycles between bus cycles, and the bus-width.
Do not access external memory other than area 0 until CSnBCR register initialization is
completed.
Bit
Bit Name
31, 30 
Initial
Value R/W
0
R
29
IWW1 1
R/W
28
IWW0 1
R/W
27

0
R
26
IWRWD1 1
R/W
25
IWRWD2 1
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Idle Cycles between Write-read Cycles and Write-write Cycles
These bits specify the number of idle cycles to be inserted
after the access to a memory that is connected to the space.
The target access cycles are the write-read cycle and write-
write cycle.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
This bit is always read as 0. The write value should always be
0.
Idle Cycles for Another Space Read-write
Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the space. The
target access cycle is a read-write one in which continuous
accesses switch between different spaces.
00: Setting prohibited
01: 2 idle cycles inserted
10: 3 idle cycles inserted
11: 5 idle cycles inserted
Rev. 2.00, 09/03, page 158 of 690