HD6417705 Datasheet, PDF (560/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 20.5 Port E Data Register (PEDR) Read/Write Operations
PECR State
PEnMD1 PEnMD0 Pin State
Read
0
0
Other function PEDR value
1
1
0
1
Note: n = 0 to 7
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
PEDR value
Pin state
Pin state
Write
Data can be written to PEDR but no effect on
pin state.
Written data is output from the pin.
Data can be written to PEDR but no effect on
pin state.
Data can be written to PEDR but no effect on
pin state.
20.6 Port F
Port F is an 8-bit input port with the pin configuration shown in figure 20.6. Each pin has an input
pull-up MOS, which is controlled by the port F control register (PFCR) in the PFC.
Port F
PTF7 (input/output)/ASEMD0 (input)
PTF6 (input/output)/ASEBRKAK (output)
PTF5 (input/output)/TDO (output)
PTF4 (input/output)/AUDSYNC (output)
PTF3 (input/output)/AUDATA3 (output)/TO3 (output)
PTF2 (input/output)/AUDATA2 (output)/TO2 (output)
PTF1 (input/output)/AUDATA1 (output)/TO1 (output)
PTF0 (input/output)/AUDATA0 (output)/TO0 (output)
Figure 20.6 Port F
20.6.1 Register Description
Port F has the following register. For details on the register address and access size, see section 24,
List of Registers.
• Port F data register (PFDR)
20.6.2 Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores data for pins PTF7 to PTF0. Bits PF7DT to
PF0DT correspond to pins PTF7 to PTF0. When the pin function is general output port, if the port
is read, the value of the corresponding PFDR bit is returned directly. When the function is general
input port, if the port is read the corresponding pin level is read.
Rev. 2.00, 09/03, page 514 of 690