HD6417705 Datasheet, PDF (351/739 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

c. Canceling software standby by manual reset
Oscillation stops
Reset
CKIO
RESETM^*1
STATUS Normal^*4
Standby^*3
Reset^*2 Normal^*4
0 to 20 Bcyc^*5
Notes: 1. When software standby mode is cleared with a manual reset, the WDT does not count.
Keep RESETM low during the PLL’s oscillation settling time.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Standby: LH (STATUS1 low, STATUS0 high)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc: Bus clock cycle
Figure 11.6 Canceling Software Standby by Manual Reset STATUS Output
In Case of Canceling Sleep:
a. Canceling sleep to interrupt
CKIO
Interrupt request
STATUS
Normal^*2
Sleep^*1
Normal*²
Notes: 1. Sleep: HL (STATUS1 high, STATUS0 low)
2. Normal: LL (STATUS1 low, STATUS0 low)
Figure 11.7 Canceling Sleep by Interrupt STATUS Output
Rev. 2.00, 09/03, page 305 of 690